Making Charged Device Model (CDM) type measurements on an integrated circuit (IC) with Very Fast TLP system test pulses requires a method to secure the IC in a location while making a low parasitic inductance electrical connection to one of its pins. The present specification describes a physical method to connect an electrical system to one pin of an IC and secure it while measuring its electrical parameters in sub-nanosecond times.
Commercial CDM testers hold an IC “dead bug” style on a metal plate and place a ground plane parallel to the ground plane above it with a coaxial cable and a compressible contact pin (known as a “pogo pin” in the electronics industry) connected to the inner conductor of the coaxial cable. A fast response one-ohm resistor is placed at the junction between the pogo pin and the inner conductor of the coaxial cable to act as a current sensor and monitor pulse discharge currents. The ground plane and pogo pin are moved down to make contact with a charged IC to discharge one pin of the IC and measure its discharge current. This test is continued to analyze each pin on the IC to determine the lowest voltage where failure occurs.
Very Fast Transmission Line Pulse (VFTLP) systems use a charged transmission line that is discharged to generate a rectangular pulse with a very fast rise time. The test pulse rise time in VFTLP can be as fast as 50 picoseconds, and can be slower than 1000 picoseconds.
VFTLP test systems simulate the rise time and width of CDM events to identify electrical characteristics of protection circuits. The present invention provides a ground plane upon which an IC is placed near a conductor that applies very fast rising pulses to a pin of the integrated circuit and measures its current and voltage response to the pulse applied from the outside of the IC. This test can identify two fundamentally different parameters based upon current and voltage measurements of the IC.
To obtain such information, the VFTLP system measures the resulting voltage and current response to these pulses by two methods. The original measurement averages the measured I-V data over a time window part way through the test pulse, after the semiconductor conductivity has reached its steady state condition and settled down for a nanosecond or more. The IC is held down to the ground plane and the current pulse from a controlled source impedance is conducted into the pin being tested to form an exponentially decaying current discharge. The exponential discharge rate is determined by the capacitance of the IC internal connections through the package insulation to the metal ground plane upon which it sits.
The second measured parameter of the IC using the VFTLP is the rate the semiconductor conductivity increases immediately after the test pulse is applied to the IC. Such measurement identifies how rapidly the semiconductor reaches its steady state conduction condition.
While the conduction is increasing it produces a significant voltage overshoot, which is the primary threat to the thin gate oxides used in modern IC's. The voltage impulse threat can be approximately measured in the early part of the pulse before the voltage charge increases as the current decreases. The time can be from a fraction of a nanosecond to a few nanoseconds, and is increasingly becoming important information in CDM design technology.
VFTLP systems typically use the commonly available 50 ohm characteristic impedance coaxial cables, connectors and the accessories used to generate, transfer, and measure the current and voltage (I-V) waveforms. The time varying current and voltage of the semiconductor circuit/s on a silicon chip inside an IC package is identified by applying different amplitude, fast-rising pulses to the DUT (“device under test”) and measuring the current and voltage reflected from it. For very fast time domain measurements, the coaxial cable connection to the DUT must have very low parasitic inductance.